Solid-state electronic devices (e.g., semiconductor “chips” or “dies”) are typically manufactured from a semiconductor material such as silicon, germanium arsenide, or gallium arsenide. Circuitry is formed on one surface, and includes input and output (“I/O”) pads to facilitate electrical connection to other circuit components.
Semiconductor chips are usually packaged for protection from mechanical damage, external contamination, and moisture. Typically, packages encapsulate the semiconductor chips within a polymeric or ceramic material.
As the configurations of electronic products become more and more light and compact, semiconductor chip packages are increasingly required to be ever smaller and more compact as well. Packages are now nearly as small as the semiconductor chips that they enclose, giving rise to numerous chip scale package (“CSP”) configurations.
Presently, the many CSP package configurations and formats can be classified generally into four types, based on their design concepts and package structures:                (1) Leadframe based CSPs, in which the electrical connection from the chip package is accomplished by electrical wiring leads;        (2) CSPs with Rigid Substrate, in which a ceramic substrate or a rigid printed circuit board of polymer material is applied in between the bare chip and the package housing structure;        (3) CSPs with Flexible Substrate, in which a soft substrate (e.g., polyimide) is used as a carrier, and an elastomer is inserted between the chip and the substrate to decrease stress; and        (4) Wafer-level CSPs, in which the carrier substrate is usually a wafer, the sizes of the packages are almost the same as the sizes of the chips, and electrical connections are by solder bump techniques similar to that of flip-chips.        
Electronic packaging techniques, for example systems-in-package (“SiP”) that use such wafer level CSP formats, thus face ever-increasing demands. The ability to use large-sized solder bumps at the wafer level has in fact become a critical focus in modern semiconductor packaging. Different techniques, such as direct placement of large solder balls, are known and available. But due to high equipment costs and high solder sphere costs, available techniques result in excessive total package costs.
Thus, a need still remains for less expensive solutions to create large solder bumps in wafer-level CSPs. Further, there is a need to accomplish these solutions using existing processes and equipment to minimize equipment costs, fabrication steps, process cycle times, and overall manufacturing costs. It is also important to be able to use existing materials in order to avoid the high costs of new, specialized, exotic materials. In view of the increasing needs for smaller, less expensive, yet more robust semiconductor package configurations, it is increasingly critical that answers be found to these problems.
Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.